1. Technical Field
The present invention relates to a test apparatus, a circuit and an electronic device. More particularly, the present invention relates to a test apparatus, a circuit and an electronic device which are designed to adjust the phase of a clock signal. The present application relates to the following international patent application. The contents of the patent application identified below are incorporated by reference herein, if applicable.
PCT/JP2006/309097 filed on May 1, 2006
2. Related Art
In recent years, semiconductor memories which can be accessed at a high speed have been increasingly configured by employing source synchronous clocking. Such a semiconductor memory is designed to generate therein not only a data signal but also a clock signal synchronized to the data signal. An external device reads the data signal in synchronization with the clock signal, which enables high-speed and efficient access to the semiconductor memory.
No relative art documents have been realized so far, and are therefore listed herein.
When testing such a semiconductor memory, a conventional test apparatus adjusts a reference clock signal for testing so as to be in synchronization with the clock signal obtained from the semiconductor memory. The test apparatus subsequently performs a test to examine whether to be capable of reading the data signal in accordance with the adjusted reference clock signal. Also, the test apparatus intentionally generates a delay in the reference clock signal by using a strobe signal, to perform another test to examine whether to be capable of reading the data when the delay takes a value within a reference range.
Here, jitter may be generated in the data signal generated by the semiconductor memory. When jitter is generated in the data signal, it is highly likely that similar jitter is generated in the clock signal generated by the semiconductor memory. Here, however, once adjusted, the reference clock signal of the conventional test apparatus is not affected by the jitter generated in the clock signal. Consequently, the generated jitter may cause a phase difference to occur between the reference clock signal and data signal, which may lower the accuracy of the test.